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Microchip Technology /ATSAMD51J20A /SDHC0 /CC2R

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Interpret as CC2R

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NOEFFECT)FSDCLKD

FSDCLKD=NOEFFECT

Description

Clock Control 2

Fields

FSDCLKD

Force SDCK Disabled

0 (NOEFFECT): No effect

1 (DISABLE): SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data